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GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
13 years 10 months ago
A design methodology for temperature variation insensitive low power circuits
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
Ranjith Kumar, Volkan Kursun
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar