38 search results - page 7 / 8 » glvlsi 2007 |
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS ad...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...