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TIM
2010
294views Education» more  TIM 2010»
13 years 10 days ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
TSMC
2010
13 years 9 days ago
A Benchmark Diagnostic Model Generation System
Abstract--It is critical to use automated generators for synthetic models and data, given the sparsity of benchmark models for empirical analysis and the cost of generating models ...
Jun Wang, Gregory M. Provan
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 10 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
EAAI
2006
189views more  EAAI 2006»
13 years 5 months ago
Evolutionary algorithms for VLSI multi-objective netlist partitioning
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Aba...
TCAD
2010
150views more  TCAD 2010»
13 years 10 days ago
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process paramete...
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Vi...