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ISCA
2011
IEEE
273views Hardware» more  ISCA 2011»
12 years 8 months ago
Bypass and insertion algorithms for exclusive last-level caches
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramone...
ISCA
2011
IEEE
225views Hardware» more  ISCA 2011»
12 years 8 months ago
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...
Rishi Agarwal, Josep Torrellas
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
12 years 8 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
12 years 8 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
12 years 8 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti