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DATE
2008
IEEE
76views Hardware» more  DATE 2008»
14 years 7 days ago
Signal Probability Based Statistical Timing Analysis
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
Bao Liu
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
14 years 5 days ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
VTS
2008
IEEE
77views Hardware» more  VTS 2008»
14 years 4 days ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
AAAI
2008
13 years 8 months ago
Computing Minimal Diagnoses by Greedy Stochastic Search
Most algorithms for computing diagnoses within a modelbased diagnosis framework are deterministic. Such algorithms guarantee soundness and completeness, but are P 2 hard. To overc...
Alexander Feldman, Gregory M. Provan, Arjan J. C. ...
AICCSA
2008
IEEE
209views Hardware» more  AICCSA 2008»
13 years 7 months ago
Transistor-level based defect tolerance for reliable nanoelectronics
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant ...
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Mel...