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ISCAS
2011
IEEE
342views Hardware» more  ISCAS 2011»
12 years 9 months ago
Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
—Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS...
Ying-Xun Lai, Yueh-Min Huang, Chin-Feng Lai, Ljilj...
ISCA
2011
IEEE
324views Hardware» more  ISCA 2011»
12 years 9 months ago
Prefetch-aware shared resource management for multi-core systems
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
ISCAS
2011
IEEE
217views Hardware» more  ISCAS 2011»
12 years 9 months ago
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC
— A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigmadelta ADC employs feed-forward architecture with oversampling rati...
Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-J...
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
12 years 9 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
12 years 9 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...