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ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...