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ISQED
2009
IEEE
115views Hardware» more  ISQED 2009»
13 years 11 months ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addres...
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
ISQED
2009
IEEE
328views Hardware» more  ISQED 2009»
13 years 11 months ago
VLSI architectures of perceptual based video watermarking for real-time copyright protection
For effective digital rights management (DRM) of multimedia in the framework of embedded systems, both watermarking and cryptography are necessary. In this paper, we present a wat...
Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manis...
ISQED
2009
IEEE
70views Hardware» more  ISQED 2009»
13 years 11 months ago
On-chip transistor characterization arrays with digital interfaces for variability characterization
An on-chip test-and-measurement system with digital interfaces that can perform device-level characterization of large-dense arrays of transistors is demonstrated in 90- and 65-nm...
Simeon Realov, William McLaughlin, Kenneth L. Shep...
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
13 years 11 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
ISQED
2009
IEEE
136views Hardware» more  ISQED 2009»
13 years 11 months ago
NBTI aware workload balancing in multi-core systems
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet ...