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ISVLSI
2005
IEEE
95views VLSI» more  ISVLSI 2005»
13 years 10 months ago
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures
Vijaykumar Ramamurthi, Jason McCollum, Christopher...
ISVLSI
2005
IEEE
102views VLSI» more  ISVLSI 2005»
13 years 10 months ago
Bi-Direction Synthesis for Reversible Circuits
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...
ISVLSI
2005
IEEE
113views VLSI» more  ISVLSI 2005»
13 years 10 months ago
Balancing System Level Pipelines with Stage Voltage Scaling
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in...
Hui Guo, Sri Parameswaran
ISVLSI
2005
IEEE
100views VLSI» more  ISVLSI 2005»
13 years 10 months ago
A Comparative Study on Dicing of Multiple Project Wafers
This paper carries out a comparative study on the methods of dicing multi-project wafers (MPW). Our dicing method results in using 40% fewer wafers both for low and high volume pr...
Meng-Chiou Wu, Rung-Bin Lin
ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
13 years 10 months ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri