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ITC
2002
IEEE
94views Hardware» more  ITC 2002»
13 years 9 months ago
Techniques to Reduce Data Volume and Application Time for Transition Test
1 Scan based transition tests are added to improve the detection of speed failures using scan tests. Empirical data suggests that both data volume and application time, for transi...
Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, P...
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
13 years 9 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ITC
2002
IEEE
72views Hardware» more  ITC 2002»
13 years 9 months ago
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
M. J. Geuzebroek, J. Th. van der Linden, A. J. van...
ATS
2004
IEEE
108views Hardware» more  ATS 2004»
13 years 8 months ago
Rapid and Energy-Efficient Testing for Embedded Cores
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 1 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...