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MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...