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TCAD
2010
88views more  TCAD 2010»
12 years 12 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
TCAD
2010
97views more  TCAD 2010»
12 years 12 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
TCAD
2010
194views more  TCAD 2010»
12 years 12 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
TCAD
2010
124views more  TCAD 2010»
12 years 12 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
TCAD
2010
160views more  TCAD 2010»
12 years 12 months ago
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...