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ISCAS
2008
IEEE
123views Hardware» more  ISCAS 2008»
13 years 11 months ago
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
—A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorith...
Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chi...
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
13 years 11 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
SASP
2008
IEEE
94views Hardware» more  SASP 2008»
13 years 11 months ago
An MDCT Hardware Accelerator for MP3 Audio
— With the increasing popularity of MP3 audio, there is a need to develop cost and power efficient architectures for the MP3 encoder and decoder. This paper describes dedicated ...
Xingdong Dai, Meghanad D. Wagh
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
TVLSI
2008
108views more  TVLSI 2008»
13 years 5 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu