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ICCAD
2007
IEEE
122views Hardware» more  ICCAD 2007»
14 years 1 months ago
Engineering change using spare cells with constant insertion
—In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referre...
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgo...
ICCAD
2007
IEEE
135views Hardware» more  ICCAD 2007»
14 years 1 months ago
A selective pattern-compression scheme for power and test-data reduction
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
Chia-Yi Lin, Hung-Ming Chen
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 1 months ago
Parameterized model order reduction via a two-directional Arnoldi process
Abstract—This paper presents a multiparameter momentmatching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi pro...
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
ICCAD
2007
IEEE
143views Hardware» more  ICCAD 2007»
14 years 1 months ago
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
—As the 193nm lithography is likely to be used for 45nm and even 32nm processes, much more stringent requirement will be posed on Optical Proximity Correction (OPC) technologies....
Peng Yu, David Z. Pan
ICCAD
2007
IEEE
64views Hardware» more  ICCAD 2007»
14 years 1 months ago
A simultaneous bus orientation and bused pin flipping algorithm
— The orientation of a bus is defined as the direction from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). Bused pin flipping is a property that allows severa...
Fan Mo, Robert K. Brayton
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 1 months ago
Temperature-aware test scheduling for multiprocessor systems-on-chip
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
David R. Bild, Sanchit Misra, Thidapat Chantem, Pr...
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 1 months ago
Scalable and scalably-verifiable sequential synthesis
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
Alan Mishchenko, Michael L. Case, Robert K. Brayto...
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
14 years 1 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
ICCAD
2008
IEEE
86views Hardware» more  ICCAD 2008»
14 years 1 months ago
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Yu Hu, Zhe Feng 0002, Lei He, Rupak Majumdar
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 1 months ago
Hardware protection and authentication through netlist level obfuscation
—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect...
Rajat Subhra Chakraborty, Swarup Bhunia