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ICCAD
2008
IEEE
223views Hardware» more  ICCAD 2008»
14 years 1 months ago
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
Takashi Enami, Masanori Hashimoto, Takashi Sato
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 1 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 1 months ago
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Ch...
ICCAD
2008
IEEE
177views Hardware» more  ICCAD 2008»
14 years 1 months ago
Double patterning technology friendly detailed routing
— Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, ...
Minsik Cho, Yongchan Ban, David Z. Pan
ICCAD
2008
IEEE
87views Hardware» more  ICCAD 2008»
14 years 1 months ago
Routing for chip-package-board co-design considering differential pairs
Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang
ICCAD
2008
IEEE
115views Hardware» more  ICCAD 2008»
14 years 1 months ago
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
Mohammad Ghasemazar, Massoud Pedram
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
14 years 1 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 1 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 1 months ago
Boolean factoring and decomposition of logic networks
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut based view of a logic network, 2) exploiting th...
Alan Mishchenko, Robert K. Brayton, Satrajit Chatt...