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ICCD
2005
IEEE
91views Hardware» more  ICCD 2005»
4 years 5 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
ICCD
2005
IEEE
95views Hardware» more  ICCD 2005»
4 years 5 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
ICCD
2005
IEEE
99views Hardware» more  ICCD 2005»
4 years 5 months ago
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhu...
ICCD
2005
IEEE
92views Hardware» more  ICCD 2005»
4 years 5 months ago
Near-memory Caching for Improved Energy Consumption
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mos...
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
4 years 5 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ICCD
2006
IEEE
91views Hardware» more  ICCD 2006»
4 years 5 months ago
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
Nathan Sadler, Daniel Sorin
ICCD
2006
IEEE
111views Hardware» more  ICCD 2006»
4 years 5 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCD
2006
IEEE
102views Hardware» more  ICCD 2006»
4 years 5 months ago
Power Droop Testing
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd...
ICCD
2006
IEEE
153views Hardware» more  ICCD 2006»
4 years 5 months ago
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...
Sanjay Pant, David Blaauw
ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
4 years 5 months ago
Reduction of Crosstalk Pessimism using Tendency Graph Approach
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...
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