GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
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GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...