Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
ASAP
2000
IEEE
163views Hardware» more  ASAP 2000»
10 years 7 months ago
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers
Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. ...
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
10 years 7 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ASAP
2000
IEEE
141views Hardware» more  ASAP 2000»
10 years 8 months ago
Bit Permutation Instructions for Accelerating Software Cryptography
Permutation is widely used in cryptographic algorithms. However, it is not well-supported in existing instruction sets. In this paper, two instructions, PPERM3R and GRP, are propo...
Zhijie Shi, Ruby B. Lee
ASAP
2000
IEEE
96views Hardware» more  ASAP 2000»
10 years 8 months ago
High-Level Synthesis of Nonprogrammable Hardware Accelerators
Robert Schreiber, Shail Aditya, B. Ramakrishna Rau...
ASAP
2000
IEEE
110views Hardware» more  ASAP 2000»
10 years 8 months ago
Compiling Image Processing Applications to Reconfigurable Hardware
Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A....
ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
10 years 8 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
ASAP
2000
IEEE
121views Hardware» more  ASAP 2000»
10 years 8 months ago
A Hardware Algorithm for Variable-Precision Logarithm
This paper presents an e cient hardware algorithm for variable-precision logarithm. The algorithm uses an iterative te chnique that employs table lookups and polynomial approximat...
Javier Hormigo, Julio Villalba, Michael J. Schulte
ASAP
2000
IEEE
90views Hardware» more  ASAP 2000»
10 years 8 months ago
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
Ruby B. Lee
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
10 years 8 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
10 years 8 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
books