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ATS
2003
IEEE
91views Hardware» more  ATS 2003»
8 years 9 months ago
An On-Chip Jitter Measurement Circuit for the PLL
Chin-Cheng Tsai, Chung-Len Lee
ATS
2003
IEEE
100views Hardware» more  ATS 2003»
8 years 9 months ago
A Processor-Based Built-In Self-Repair Design for Embedded Memories
We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost...
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
ATS
2003
IEEE
112views Hardware» more  ATS 2003»
8 years 11 months ago
Domain Testing Based on Character String Predicate
Domain testing is a well-known software testing technique. Although research tasks have been initiated in domain testing, automatic test data generation based on character string ...
Ruilian Zhao, Michael R. Lyu, Yinghua Min
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
8 years 11 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
ATS
2003
IEEE
105views Hardware» more  ATS 2003»
8 years 11 months ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
8 years 11 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
8 years 11 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ATS
2003
IEEE
151views Hardware» more  ATS 2003»
8 years 11 months ago
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
Junhao Shi, Görschwin Fey, Rolf Drechsler
ATS
2003
IEEE
110views Hardware» more  ATS 2003»
8 years 11 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
8 years 11 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
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