ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of rev...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...