clock network minimization

ASPDAC
2005
ACM

127views Hardware» more ASPDAC 2005»

Clock network minimization methodology based on incremental placement

13 years 10 months ago

: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...

Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...

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DAC
2005
ACM

106views Computer Architecture» more DAC 2005»

Navigating registers in placement for clock network minimization

14 years 5 months ago

Download dropzone.tamu.edu

Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...

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