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CODES
2005
IEEE
9 years 9 months ago
A core flight software system
No two flight missions are alike, hence, development and on-orbit software costs are high. Software portability and adaptability across hardware platforms and operating systems ha...
Jonathan Wilmot
CODES
2005
IEEE
9 years 9 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
CODES
2005
IEEE
9 years 9 months ago
Developing design tools for biological and biomedical applications of micro- and nano-technology
This short paper, an update of [75], is intended to provide a brief summary and extensive references on biological applications for micro- and nano-machining, as well as the compu...
Jacob White
CODES
2005
IEEE
9 years 9 months ago
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
The performance of virtual machines (e.g., Java Virtual Machines—JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from...
Miljan Vuletic, Christophe Dubach, Laura Pozzi, Pa...
CODES
2005
IEEE
9 years 9 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
CODES
2005
IEEE
9 years 9 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
CODES
2005
IEEE
9 years 9 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CODES
2005
IEEE
9 years 9 months ago
Automatic network generation for system-on-chip communication design
With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary....
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CODES
2005
IEEE
9 years 9 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
CODES
2005
IEEE
9 years 9 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
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