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CSREAESA
2006
10 years 1 months ago
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs
Abstract
Daniel T. Milton, Sachin Dhingra, Charles E. Strou...
CSREAESA
2006
10 years 1 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
CSREAESA
2006
10 years 1 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
CSREAESA
2006
10 years 1 months ago
The Satellite Data Model
The Satellite Data Model (SDM) is part of the Air Force Research Laboratory (AFRL) Responsive Space Testbed Initiative. It is a developing standard for rapid integration of hardwa...
Kenneth Sundberg, Scott Cannon, Todd Hospodarsky, ...
CSREAESA
2006
10 years 1 months ago
Layered Architecture Revised
- A systematic approach to building layered software architecture is proposed. Separate layering models required oper abstracting of hardware, persistent data, and communication pr...
Asher Sterkin
CSREAESA
2006
10 years 1 months ago
In-House Built Bipedal Walking Robot
In this project, an in-house built bipedal walking Robot uses two direct current gear motors to power its legs. Each leg could bend at the knee to assist the walking routines. In ...
Kok-Swee Sim, Yee Kin Lum, Chih Ping Tso
CSREAESA
2006
10 years 1 months ago
Static Program Partitioning for Embedded Processors
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
Bageshri Sathe, Uday P. Khedker
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