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MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
8 years 8 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
ASPLOS
1998
ACM
8 years 8 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
8 years 8 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ICS
2001
Tsinghua U.
8 years 8 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
8 years 9 months ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
8 years 9 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
8 years 9 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
ICDE
2003
IEEE
208views Database» more  ICDE 2003»
8 years 9 months ago
DBProxy: A dynamic data cache for Web applications
The majority of web pages served today are generated dynamically, usually by an application server querying a back-end database. To enhance the scalability of dynamic content serv...
Khalil Amiri, Sanghyun Park, Renu Tewari, Sriram P...
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
8 years 9 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
CODES
2003
IEEE
8 years 9 months ago
Tracking object life cycle for leakage energy optimization
The focus of this work is on utilizing the state of objects during their lifespan in optimizing the leakage energy consumed in the data caches when executing embedded Java applica...
Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. K...
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