Sciweavers

DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 10 months ago
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition
This paper addresses two problems related to disjointsupport decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results...
Andrés Martinelli, Elena Dubrova
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
13 years 10 months ago
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communica...
Philippe Martin
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 10 months ago
Uniformly-Switching Logic for Cryptographic Hardware
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
Igor L. Markov, Dmitri Maslov
DATE
2005
IEEE
235views Hardware» more  DATE 2005»
13 years 10 months ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 10 months ago
Energy Bounds for Fault-Tolerant Nanoscale Designs
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
Diana Marculescu
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
13 years 10 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...
DATE
2005
IEEE
176views Hardware» more  DATE 2005»
13 years 10 months ago
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
Linear Pseudo-Boolean Optimization (PBO) is a widely used modeling framework in Electronic Design Automation (EDA). Due to significant advances in Boolean Satisfiability (SAT), ...
Vasco M. Manquinho, João P. Marques Silva
DATE
2005
IEEE
88views Hardware» more  DATE 2005»
13 years 10 months ago
System Synthesis for Networks of Programmable Blocks
The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor ...
Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank ...
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
13 years 10 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
13 years 10 months ago
New Perspectives and Opportunities From the Wild West of Microelectronic Biochips
Application of Microelectronic to bioanalysis is an emerging field which holds great promise. From the standpoint of electronic and system design, biochips imply a radical change ...
Nicolò Manaresi, Gianni Medoro, Melanie Abo...