DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parame...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construc...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication. The parasitic inductance within IC packaging causes bounce o...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Unified Modeling Language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-Profile - that introduces a set of st...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
DATE
2005
IEEE
2005
IEEE
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
13 years 10 months ago
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...