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DATE
2006
IEEE
107views Hardware» more  DATE 2006»
13 years 10 months ago
Disjunctive image computation for embedded software verification
Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gup...
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
13 years 10 months ago
On-chip bus thermal analysis and optimization
As technology scales, increasing clock rates, decreasing
Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan,...
DATE
2006
IEEE
71views Hardware» more  DATE 2006»
13 years 10 months ago
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
This paper derives the multi-layer heat conduction Green’s function, by integrating the eigen-expansion technique and the classic transmission line theories, and presents a loga...
Baohua Wang, Pinaki Mazumder
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
13 years 10 months ago
Test set enrichment using a probabilistic fault model and the theory of output deviations
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
13 years 10 months ago
Efficient unknown blocking using LFSR reseeding
Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat ...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
13 years 10 months ago
Performance analysis of greedy shapers in real-time systems
— Traffic shaping is a well-known technique in the area of networking and is proven to reduce global buffer requirements and end-to-end delays in networked systems. Due to these...
Ernesto Wandeler, Alexander Maxiaguine, Lothar Thi...
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
13 years 10 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
13 years 10 months ago
Formal performance analysis and simulation of UML/SysML models for ESL design
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative perfo...
Alexander Viehl, Timo Schönwald, Oliver Bring...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
13 years 10 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
13 years 10 months ago
Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses
Hans Vandierendonck, Philippe Manet, Jean-Didier L...