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DATE
2008
IEEE
119views Hardware» more  DATE 2008»
13 years 11 months ago
Process Variation Aware Issue Queue Design
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
Raghavendra K, Madhu Mutyam
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
13 years 11 months ago
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis
Fabiano Cruz, Raimundo S. Barreto, Lucas Cordeiro,...
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
13 years 11 months ago
Incremental Criticality and Yield Gradients
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
DATE
2008
IEEE
82views Hardware» more  DATE 2008»
13 years 11 months ago
Variation tolerant NoC design by means of self-calibrating links
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC ar...
Simone Medardoni, Marcello Lajolo, Davide Bertozzi
DATE
2008
IEEE
95views Hardware» more  DATE 2008»
13 years 11 months ago
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
Constant-coefficient multipliers are fundamental components in digital signal processing and arithmetic-based systems. Their verification, however, remains difficult and time-cons...
Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo
DATE
2008
IEEE
69views Hardware» more  DATE 2008»
13 years 11 months ago
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme
Token passing is a channel access technique used in several communication networks. Among them, one of the most effective solution for supporting both real-time traffic (synchron...
Gianluca Franchino, Giorgio C. Buttazzo, Tullio Fa...
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
13 years 11 months ago
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...
DATE
2008
IEEE
66views Hardware» more  DATE 2008»
13 years 11 months ago
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
Tomokazu Yoneda, Hideo Fujiwara