Sciweavers

DAC
2005
ACM
14 years 5 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
DAC
2005
ACM
14 years 5 months ago
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
King Ho Tam, Lei He
DAC
2005
ACM
14 years 5 months ago
Path based buffer insertion
Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weip...
DAC
2005
ACM
14 years 5 months ago
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
DAC
2005
ACM
14 years 5 months ago
A quasi-convex optimization approach to parameterized model order reduction
In this paper an optimization based model order reduction (MOR) framework is proposed. The method involves setting up a quasiconvex program that explicitly minimizes a relaxation ...
Kin Cheong Sou, Alexandre Megretski, Luca Daniel
DAC
2005
ACM
14 years 5 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
DAC
2005
ACM
14 years 5 months ago
Incremental retiming for FPGA physical synthesis
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...
DAC
2005
ACM
14 years 5 months ago
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
DAC
2005
ACM
14 years 5 months ago
Multi-threaded reachability
Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. Such algorithms can be at times ineffective ...
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer,...