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    DAC
    2006
    ACM
    107views Computer Architecture» more  DAC 2006»
    Timing-driven Steiner trees are (practically) free
    14 years 5 months ago
    Timing-driven Steiner trees are (practically) free
    Download  vlsicad.ucsd.edu
    Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...
    Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sz...
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    DAC
    2006
    ACM
    84views Computer Architecture» more  DAC 2006»
    A family of cells to reduce the soft-error-rate in ternary-CAM
    14 years 5 months ago
    A family of cells to reduce the soft-error-rate in ternary-CAM
    Download  www.eecg.toronto.edu
    Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
    Navid Azizi, Farid N. Najm
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    DAC
    2005
    ACM
    102views Computer Architecture» more  DAC 2005»
    Structure preserving reduction of frequency-dependent interconnect
    14 years 5 months ago
    Structure preserving reduction of frequency-dependent interconnect
    Download  www.ece.rice.edu
    A rational Arnoldi method for passivity-preserving model-order reduction (MOR) with implicit multi-point moment matching for systems with frequency-dependent interconnects is desc...
    Quming Zhou, Kartik Mohanram, Athanasios C. Antoul...
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    DAC
    2005
    ACM
    97views Computer Architecture» more  DAC 2005»
    Optimal procrastinating voltage scheduling for hard real-time systems
    14 years 5 months ago
    Optimal procrastinating voltage scheduling for hard real-time systems
    Download  www.cs.virginia.edu
    This paper presents an optimal procrastinating voltage scheduling (OP-DVS) for hard real-time systems using stochastic workload information. Algorithms are presented for both sing...
    Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, M...
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    DAC
    2005
    ACM
    110views Computer Architecture» more  DAC 2005»
    High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
    14 years 5 months ago
    High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
    Download  users.ece.utexas.edu
    Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
    Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...
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    DAC
    2005
    ACM
    112views Computer Architecture» more  DAC 2005»
    Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
    14 years 5 months ago
    Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
    Download  vlsi.ece.wisc.edu
    Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
    Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubn...
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    DAC
    2005
    ACM
    111views Computer Architecture» more  DAC 2005»
    Correlation-aware statistical timing analysis with non-gaussian delay distributions
    14 years 5 months ago
    Correlation-aware statistical timing analysis with non-gaussian delay distributions
    Download  www.ece.cmu.edu
    Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence...
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    DAC
    2005
    ACM
    120views Computer Architecture» more  DAC 2005»
    System-level energy-efficient dynamic task scheduling
    14 years 5 months ago
    System-level energy-efficient dynamic task scheduling
    Download  www.public.asu.edu
    Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
    Jianli Zhuo, Chaitali Chakrabarti
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    DAC
    2005
    ACM
    176views Computer Architecture» more  DAC 2005»
    Enhanced leakage reduction Technique by gate replacement
    14 years 5 months ago
    Enhanced leakage reduction Technique by gate replacement
    Download  www.ece.umd.edu
    Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
    Lin Yuan, Gang Qu
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    DAC
    2005
    ACM
    93views Computer Architecture» more  DAC 2005»
    Secure scan: a design-for-test architecture for crypto chips
    14 years 5 months ago
    Secure scan: a design-for-test architecture for crypto chips
    Download  www.inf.ethz.ch
    Bo Yang, Kaijie Wu, Ramesh Karri
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