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    DAC
    2006
    ACM
    100views Computer Architecture» more  DAC 2006»
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus
    14 years 5 months ago
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus
    Download  www.lirmm.fr
    This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
    Reouven Elbaz, Lionel Torres, Gilles Sassatelli, P...
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    DAC
    2006
    ACM
    116views Computer Architecture» more  DAC 2006»
    Transistor abstraction for the functional verification of FPGAs
    14 years 5 months ago
    Transistor abstraction for the functional verification of FPGAs
    Download  www.altera.com
    or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
    Guy Dupenloup, Thierry Lemeunier, Roland Mayr
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    DAC
    2006
    ACM
    112views Computer Architecture» more  DAC 2006»
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
    14 years 5 months ago
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
    Download  www.ece.ucsb.edu
    Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
    Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
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    DAC
    2006
    ACM
    132views Computer Architecture» more  DAC 2006»
    Synthesis of synchronous elastic architectures
    14 years 5 months ago
    Synthesis of synchronous elastic architectures
    Download  www.lsi.upc.edu
    A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automat...
    Jordi Cortadella, Michael Kishinevsky, Bill Grundm...
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    DAC
    2006
    ACM
    150views Computer Architecture» more  DAC 2006»
    An efficient and versatile scheduling algorithm based on SDC formulation
    14 years 5 months ago
    An efficient and versatile scheduling algorithm based on SDC formulation
    Download  cadlab.cs.ucla.edu
    Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
    Jason Cong, Zhiru Zhang
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    DAC
    2006
    ACM
    187views Computer Architecture» more  DAC 2006»
    Behavior and communication co-optimization for systems with sequential communication media
    14 years 5 months ago
    Behavior and communication co-optimization for systems with sequential communication media
    Download  cadlab.cs.ucla.edu
    In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
    Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
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    DAC
    2006
    ACM
    160views Computer Architecture» more  DAC 2006»
    BoxRouter: a new global router based on box expansion and progressive ILP
    14 years 5 months ago
    BoxRouter: a new global router based on box expansion and progressive ILP
    Download  www.cerc.utexas.edu
    In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion and progressive integer linear programming (ILP). BoxRouter first uses a simple P...
    Minsik Cho, David Z. Pan
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    DAC
    2006
    ACM
    155views Computer Architecture» more  DAC 2006»
    High-level power management of embedded systems with application-specific energy cost functions
    14 years 5 months ago
    High-level power management of embedded systems with application-specific energy cost functions
    Download  elpl.snu.ac.kr
    Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
    Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti...
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    DAC
    2006
    ACM
    109views Computer Architecture» more  DAC 2006»
    Timing driven power gating
    14 years 5 months ago
    Timing driven power gating
    Download  cad63.cs.nthu.edu.tw
    Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
    De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...
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    DAC
    2006
    ACM
    105views Computer Architecture» more  DAC 2006»
    A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
    14 years 5 months ago
    A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
    Download  icims.csl.uiuc.edu
    Lei Cheng, Liang Deng, Deming Chen, Martin D. F. W...
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