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TCAD
2010
164views more  TCAD 2010»
13 years 4 months ago
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
Javid Jaffari, Mohab Anis
ENTCS
2010
113views more  ENTCS 2010»
13 years 9 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
Dan R. Ghica, Alex Smith
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
13 years 9 months ago
RobuCheck: A Robustness Checker for Digital Circuits
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
Stefan Frehse, Görschwin Fey, André S&...
CSREAESA
2003
13 years 10 months ago
Design of Digital Circuits on the Basis of Hardware Templates
The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
Valery Sklyarov, Iouliia Skliarova
ITC
1995
IEEE
122views Hardware» more  ITC 1995»
14 years 27 days ago
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
Stefan Weiner
EH
2004
IEEE
107views Hardware» more  EH 2004»
14 years 1 months ago
Evolving Digital Circuits using Multi Expression Programming
Multi Expression Programming (MEP) is a Genetic Programming (GP) variant that uses linear chromosomes for solution encoding. A unique MEP feature is its ability of encoding multipl...
Mihai Oltean, Crina Grosan
DAC
1990
ACM
14 years 1 months ago
Timing Verification Using HDTV
In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the ne...
Alan R. Martello, Steven P. Levitan, Donald M. Chi...
CCL
1994
Springer
14 years 1 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 2 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
FM
2003
Springer
107views Formal Methods» more  FM 2003»
14 years 2 months ago
A Formal Framework for Modular Synchronous System Design
We present the formal framework for a novel approach for specifying and automatically implementing systems such as digital circuits and network protocols. The goal is to reduce the...
Maria-Cristina V. Marinescu, Martin C. Rinard