ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
DSN
2000
IEEE
13 years 9 months ago
2000
IEEE
In order to be able to tolerate the effects of faults, we must first detect the symptoms of faults, i.e. the errors. This paper evaluates the error detection properties of an erro...
PCM
2001
Springer
13 years 9 months ago
2001
Springer
In video communications over error introducing channels, error concealment techniques are widely applied in video decoder for good subjective images output. However, a damaged MB ...
MIDDLEWARE
2009
Springer
13 years 9 months ago
2009
Springer
Today’s distributed systems need runtime error detection to catch errors arising from software bugs, hardware errors, or unexpected operating conditions. A prominent class of err...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
IEEEMSP
2002
IEEE
13 years 9 months ago
2002
IEEE
Abstract—Transmission of digital contents in unavoidable noiseprone environments demands sophisticated error detection and concealment techniques to restore the perceptual qualit...
DSN
2002
IEEE
13 years 9 months ago
2002
IEEE
Standardized 32-bit Cyclic Redundancy Codes provide fewer bits of guaranteed error detection than they could, achieving a Hamming Distance (HD) of only 4 for maximum-length Ethern...
DSN
2002
IEEE
13 years 9 months ago
2002
IEEE
An important aspect in the development of dependable software is to decide where to locate mechanisms for efficient error detection and recovery. We present a comparison between ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in ge...
DFT
2003
IEEE
13 years 9 months ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...