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ETS
2006
IEEE
113views Hardware» more  ETS 2006»
10 years 5 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
ETS
2006
IEEE
119views Hardware» more  ETS 2006»
10 years 5 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
ETS
2006
IEEE
129views Hardware» more  ETS 2006»
10 years 5 months ago
Dynamic Voltage Scaling Aware Delay Fault Testing
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M....
ETS
2006
IEEE
100views Hardware» more  ETS 2006»
10 years 5 months ago
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun,...
ETS
2006
IEEE
108views Hardware» more  ETS 2006»
10 years 5 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...
ETS
2006
IEEE
77views Hardware» more  ETS 2006»
10 years 5 months ago
Enhancing Delay Fault Coverage through Low Power Segmented Scan
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Jan...
ETS
2006
IEEE
93views Hardware» more  ETS 2006»
10 years 5 months ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young
ETS
2006
IEEE
118views Hardware» more  ETS 2006»
10 years 5 months ago
Living with Failure: Lessons from Nature?
- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continui...
Steve Furber
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
10 years 5 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
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