Sciweavers

ITC
1998
IEEE
94views Hardware» more  ITC 1998»
13 years 9 months ago
Probabilistic mixed-model fault diagnosis
Previously-proposed strategies for VLSI fault diagnosis have su ered from a variety of self-imposed limitations. Some techniques are limited to a speci c fault model, and many wil...
David B. Lavo, Brian Chess, Tracy Larrabee, Ismed ...
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 9 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
ATS
2000
IEEE
116views Hardware» more  ATS 2000»
13 years 10 months ago
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
Said Hamdioui, A. J. van de Goor
SAFECOMP
2001
Springer
13 years 10 months ago
An Investigation on Mutation Strategies for Fault Injection into RDD-100 Models
This paper focuses on the development of a conceptual framework for integrating fault injection mechanisms into the RDD-100 tool2 to support the dependability analysis of computer...
Mohamed Kaâniche, Yannick Le Guédart,...
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
13 years 10 months ago
Modeling Techniques and Tests for Partial Faults in Memory Devices
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
Zaid Al-Ars, A. J. van de Goor
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
13 years 11 months ago
Test set enrichment using a probabilistic fault model and the theory of output deviations
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
DATE
2006
IEEE
75views Hardware» more  DATE 2006»
13 years 11 months ago
Space of DRAM fault models and corresponding testing
Abstract: DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of faul...
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
ETS
2007
IEEE
91views Hardware» more  ETS 2007»
13 years 11 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
13 years 12 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...