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VTS
2002
IEEE
101views Hardware» more  VTS 2002»
8 years 10 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
DFT
2002
IEEE
79views VLSI» more  DFT 2002»
8 years 10 months ago
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
8 years 10 months ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
8 years 10 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
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