ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
DSN
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents the experiences of using a symbolic model checker to check the safety properties of a servoloop control system. Symbolic model checking has been shown to be be...
DSD
2002
IEEE
13 years 9 months ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
ADC
2004
Springer
13 years 10 months ago
2004
Springer
Workflow technology has met with success in a variety of industries, although several limitations have emerged. One such drawback is the inflexibility of specification languages, ...
SIGCSE
2006
ACM
13 years 11 months ago
2006
ACM
Visualization and interactivity are valuable active learning techniques that can improve mastery of difficult concepts. In this paper we describe jFAST, an easy-to-use graphical s...
AICCSA
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents an encoding algorithm that is very efficient for many different logic synthesis problems. The algorithm is based on the use of special tables and includes two ...
HASE
2008
IEEE
13 years 11 months ago
2008
IEEE
For complex services, logging is an integral part of many middleware aspects, especially, transactions and monitoring. In the event of a failure, the log allows us to deduce the c...
ISCIS
2009
Springer
13 years 11 months ago
2009
Springer
—Methods for software testing based on Finite State Machines (FSMs) have been researched since the early 60’s. Many of these methods are about generating a checking sequence fr...
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Vitaliy KlebanEngineer
Saint-Petersburg State University of Information Technologies, Mechanics and Optics
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