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2000
ACM

A novel high throughput reconfigurable FPGA architecture

10 years 6 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. This architecture utilizes the concept of `WaveSteering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where FPGA
Authors Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
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