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    FPGA
    2001
    ACM
    142views FPGA» more  FPGA 2001»
    Runtime and quality tradeoffs in FPGA placement and routing
    13 years 9 months ago
    Runtime and quality tradeoffs in FPGA placement and routing
    Download  www.ee.washington.edu
    Chandra Mulpuri, Scott Hauck
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    FPGA
    2001
    ACM
    123views FPGA» more  FPGA 2001»
    Matching and searching analysis for parallel hardware implementation on FPGAs
    13 years 9 months ago
    Matching and searching analysis for parallel hardware implementation on FPGAs
    Download  www.isi.edu
    Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
    Pablo Moisset, Pedro C. Diniz, Joonseok Park
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    FPGA
    2001
    ACM
    152views FPGA» more  FPGA 2001»
    A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
    13 years 9 months ago
    A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
    Download  nirvana.informatik.uni-halle.de
    Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
    Jörg Ritter, Paul Molitor
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    FPGA
    2001
    ACM
    162views FPGA» more  FPGA 2001»
    Reprogrammable network packet processing on the field programmable port extender (FPX)
    13 years 9 months ago
    Reprogrammable network packet processing on the field programmable port extender (FPX)
    Download  www.arl.wustl.edu
    A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...
    John W. Lockwood, Naji Naufel, Jonathan S. Turner,...
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    FPGA
    2001
    ACM
    128views FPGA» more  FPGA 2001»
    Using sparse crossbars within LUT
    13 years 9 months ago
    Using sparse crossbars within LUT
    Download  www.eecg.toronto.edu
    In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, bu...
    Guy G. Lemieux, David M. Lewis
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    FPGA
    2001
    ACM
    139views FPGA» more  FPGA 2001»
    A memory coherence technique for online transient error recovery of FPGA configurations
    13 years 9 months ago
    A memory coherence technique for online transient error recovery of FPGA configurations
    Download  www-crc.stanford.edu
    The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
    Wei-Je Huang, Edward J. McCluskey
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    FPGA
    2001
    ACM
    137views FPGA» more  FPGA 2001»
    Detailed routing architectures for embedded programmable logic IP cores
    13 years 9 months ago
    Detailed routing architectures for embedded programmable logic IP cores
    Download  www.ece.ubc.ca
    As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
    Peter Hallschmid, Steven J. E. Wilton
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    FPGA
    2001
    ACM
    326views FPGA» more  FPGA 2001»
    Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
    13 years 9 months ago
    Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
    Download  www.arl.wustl.edu
    Janette Frigo, Maya Gokhale, Dominique Lavenier
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    FPGA
    2001
    ACM
    138views FPGA» more  FPGA 2001»
    Performance-driven mapping for CPLD architectures
    13 years 9 months ago
    Performance-driven mapping for CPLD architectures
    Download  cadlab.cs.ucla.edu
    Deming Chen, Jason Cong, Milos D. Ercegovac, Zhiju...
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    FPGA
    2001
    ACM
    145views FPGA» more  FPGA 2001»
    Simultaneous logic decomposition with technology mapping in FPGA designs
    13 years 9 months ago
    Simultaneous logic decomposition with technology mapping in FPGA designs
    Download  cadlab.cs.ucla.edu
    Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
    Gang Chen, Jason Cong
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