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GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
13 years 9 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2000
IEEE
82views VLSI» more  GLVLSI 2000»
13 years 9 months ago
A comparative study of power efficient SRAM designs
Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane...
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
13 years 9 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
GLVLSI
2000
IEEE
109views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Accuracy management for mixed-mode digital VLSI simulation
Gary L. Dare, Charles A. Zukowski
GLVLSI
2000
IEEE
83views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Power estimation for a submicron CMOS inverter driving a CRC interconnect load
Ï ÔÖ × ÒØ Ò Ò ÐÝØ Ð ÜÔÖ ×× ÓÒ ÓÖ Ø Ú ÐÙ Ø ÓÒ Ó Ø × ÓÖع Ö Ù Ø ÔÓÛ Ö ×× Ô Ø ÓÒ Ò ÅÇË ÒÚ ÖØ Ö Ö Ú¹ Ò Ê ÒØ Ö ÓÒÒ ...
Hung-Jung Chen, Bradley S. Carlson
GLVLSI
2000
IEEE
69views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Supporting system-level power exploration for DSP applications
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...
Luca Benini, Marco Ferrero, Alberto Macii, Enrico ...
GLVLSI
2000
IEEE
95views VLSI» more  GLVLSI 2000»
13 years 9 months ago
MCM placement using a realistic thermal model
— Typically, placement algorithms attempt to minimize the total net length of a printed circuit board (PCB). However, an MCM’s increased throughput and dense circuitry can easi...
Craig Beebe, Jo Dale Carothers, Alfonso Ortega
GLVLSI
2000
IEEE
80views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Efficient algorithms for acceptable design exploration
Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xi...
GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
13 years 9 months ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh