Fast and accurate estimation of floorplans in logic/high-level synthesis

In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of different performance measures of the chip, namely area, delay and power consumption. These measures cannot be estimated with high accuracy unless a fairly detailed layout of the chip, including the floorplan and routing is available, which in turn are very costly processes in terms of running time. As we have entered the deep sub-micron era, we have to deal with designs which contain million gates and up. Not only we should consider the area occupied by the modules, but we also have to consider the wiring congestion. In this paper we propose a cost function that is, in addition to other parameters, a function of the wiring area. We also propose a method, to avoid running the floorplanning process after every change in the design, by considering the possible changes in advance and generating a floorplan which i...

• Type: Conference
• Year: 2000
• Where: GLVLSI
• Authors: Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
• Keywords: Engineering Change Order, GLVLSI 2000, Logic Synthesis, Performance Measures, VLSI