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GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
10 years 6 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
GLVLSI
2002
IEEE
82views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Reconfigurable repetitive padding unit
Georgi Kuzmanov, Stamatis Vassiliadis
GLVLSI
2002
IEEE
135views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Low swing dual threshold voltage domino logic
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
Volkan Kursun, Eby G. Friedman
GLVLSI
2002
IEEE
118views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Novel interconnect modeling by using high-order compact finite difference methods
— The high-order compact finite difference (HCFD) method is adapted for interconnect modeling. Based on the compact finite difference method, the HCFD method employs the Chebys...
Qinwei Xu, Pinaki Mazumder
GLVLSI
2002
IEEE
80views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Selective-run built-in self-test using an embedded processor
Sungbae Hwang, Jacob A. Abraham
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
GLVLSI
2002
IEEE
95views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Term ordering problem on MDG
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
Yi Feng, Eduard Cerny
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Enhanced clustered voltage scaling for low power
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Monica Donno, Luca Macchiarulo, Alberto Macii, Enr...
GLVLSI
2002
IEEE
123views VLSI» more  GLVLSI 2002»
10 years 6 months ago
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU
Joel Grodstein, Rachid Rayess, Tad Truex, Linda Sh...
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