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GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
GLVLSI
2010
IEEE
178views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Improving the testability and reliability of sequential circuits with invariant logic
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...
GLVLSI
2010
IEEE
138views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
Emre Salman, Eby G. Friedman
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
GLVLSI
2010
IEEE
139views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Dynamically resizable binary decision diagrams
We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library’s no...
Stergios Stergiou, Jawahar Jain
GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
10 years 6 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2010
IEEE
212views VLSI» more  GLVLSI 2010»
10 years 6 months ago
An integrated thermal estimation framework for industrial embedded platforms
Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal contro...
Andrea Acquaviva, Andrea Calimera, Alberto Macii, ...
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