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HIPEAC
2009
Springer
9 years 10 months ago
Accomodating Diversity in CMPs with Heterogeneous Frequencies
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
HIPEAC
2009
Springer
9 years 10 months ago
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
Lee W. Howes, Anton Lokhmotov, Alastair F. Donalds...
HIPEAC
2009
Springer
9 years 10 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
HIPEAC
2009
Springer
9 years 10 months ago
MPSoC Design Using Application-Specific Architecturally Visible Communication
Abstract. This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide highthroughput communication for str...
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo ...
HIPEAC
2009
Springer
9 years 10 months ago
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
HIPEAC
2009
Springer
9 years 11 months ago
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
Abstract. In transactional memory, aborted transactions reduce performance, and waste computing resources. Ideally, concurrent execution of transactions should be optimally ordered...
Mohammad Ansari, Mikel Luján, Christos Kots...
HIPEAC
2009
Springer
9 years 11 months ago
Revisiting Cache Block Superloading
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
Matthew A. Watkins, Sally A. McKee, Lambert Schael...
HIPEAC
2009
Springer
10 years 1 months ago
Parallel H.264 Decoding on an Embedded Multicore Processor
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inte...
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurli...
HIPEAC
2009
Springer
10 years 1 months ago
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhou...
HIPEAC
2009
Springer
10 years 1 months ago
Collective Optimization
Abstract. Iterative compilation is an efficient approach to optimize programs on rapidly evolving hardware, but it is still only scarcely used in practice due to a necessity to gat...
Grigori Fursin, Olivier Temam
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