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ICCAD
1993
IEEE
112views Hardware» more  ICCAD 1993»
13 years 9 months ago
Piecewise linear models for Rsim
Russell Kao, Mark Horowitz
ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
13 years 9 months ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant
ICCAD
1993
IEEE
139views Hardware» more  ICCAD 1993»
13 years 9 months ago
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
Ing-Jer Huang, Alvin M. Despain
ICCAD
1993
IEEE
97views Hardware» more  ICCAD 1993»
13 years 9 months ago
High level synthesis for reconfigurable datapath structures
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
13 years 9 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
13 years 9 months ago
Instruction set mapping for performance optimization
Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerr...
ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
13 years 9 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
ICCAD
1993
IEEE
120views Hardware» more  ICCAD 1993»
13 years 9 months ago
Latchup-aware placement and parasitic-bounded routing of custom analog cells
Bulent Basaran, Rob A. Rutenbar, L. Richard Carley
ICCAD
1993
IEEE
108views Hardware» more  ICCAD 1993»
13 years 9 months ago
Exact evaluation of memory size for multi-dimensional signal processing systems
Florin Balasa, Francky Catthoor, Hugo De Man