ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Interconnectperformance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes tal abstraction necessary for high levels of integration...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. To impro...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...