ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
{ Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of
exibility, performance and power...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the prese...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...