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ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
13 years 8 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
13 years 8 months ago
An optimal algorithm for area minimization of slicing floorplans
The traditional algorithm of Stockmeyer for area minimization of slicing oorplans has time (and space) complexity O(n2 ) in the worst case, or O(nlogn) for balanced slicing. For ...
Weiping Shi
ICCAD
1995
IEEE
95views Hardware» more  ICCAD 1995»
13 years 8 months ago
A sequential quadratic programming approach to concurrent gate and wire sizing
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
Noel Menezes, Ross Baldick, Lawrence T. Pileggi
ICCAD
1995
IEEE
92views Hardware» more  ICCAD 1995»
13 years 8 months ago
Linear decomposition algorithm for VLSI design applications
Jianmin Li, John Lillis, Chung-Kuan Cheng
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
13 years 8 months ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
13 years 8 months ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
ICCAD
1995
IEEE
79views Hardware» more  ICCAD 1995»
13 years 8 months ago
Optimal wire sizing and buffer insertion for low power and a generalized delay model
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
ICCAD
1995
IEEE
108views Hardware» more  ICCAD 1995»
13 years 8 months ago
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
Haifang Liao, Wayne Wei-Ming Dai
ICCAD
1995
IEEE
167views Hardware» more  ICCAD 1995»
13 years 8 months ago
A novel methodology for statistical parameter extraction
IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf’s) or as worst case combinations/corners of the device model pa...
Kannan Krishna, Stephen W. Director