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    ICCAD
    1995
    IEEE
    68views Hardware» more  ICCAD 1995»
    Generating sparse partial inductance matrices with guaranteed stability
    13 years 8 months ago
    Generating sparse partial inductance matrices with guaranteed stability
    Download  www.cs.york.ac.uk
    This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
    Byron Krauter, Lawrence T. Pileggi
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    ICCAD
    1995
    IEEE
    61views Hardware» more  ICCAD 1995»
    Stable and efficient reduction of substrate model networks using congruence transforms
    13 years 8 months ago
    Stable and efficient reduction of substrate model networks using congruence transforms
    Download  www.cs.york.ac.uk
    Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang
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    ICCAD
    1995
    IEEE
    144views Hardware» more  ICCAD 1995»
    Background memory management for dynamic data structure intensive processing systems
    13 years 8 months ago
    Background memory management for dynamic data structure intensive processing systems
    Download  cwc.ucsd.edu
    Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
    Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
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    ICCAD
    1995
    IEEE
    120views Hardware» more  ICCAD 1995»
    Pattern generation for a deterministic BIST scheme
    13 years 8 months ago
    Pattern generation for a deterministic BIST scheme
    Download  www.ra.informatik.uni-stuttgart.de
    Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
    Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, ...
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    ICCAD
    1995
    IEEE
    134views Hardware» more  ICCAD 1995»
    A delay model for logic synthesis of continuously-sized networks
    13 years 8 months ago
    A delay model for logic synthesis of continuously-sized networks
    Download  www.cs.york.ac.uk
    ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
    Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
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    ICCAD
    1995
    IEEE
    65views Hardware» more  ICCAD 1995»
    Symbolic hazard-free minimization and encoding of asynchronous finite state machines
    13 years 8 months ago
    Symbolic hazard-free minimization and encoding of asynchronous finite state machines
    Download  www.cs.unc.edu
    Robert M. Fuhrer, Bill Lin, Steven M. Nowick
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    ICCAD
    1995
    IEEE
    97views Hardware» more  ICCAD 1995»
    APPlaUSE: Area and performance optimization in a unified placement and synthesis environment
    13 years 8 months ago
    APPlaUSE: Area and performance optimization in a unified placement and synthesis environment
    Download  www.cecs.uci.edu
    Elof Frank, Thomas Lengauer
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    ICCAD
    1995
    IEEE
    136views Hardware» more  ICCAD 1995»
    A controller-based design-for-testability technique for controller-data path circuits
    13 years 8 months ago
    A controller-based design-for-testability technique for controller-data path circuits
    Download  www.cs.ucla.edu
    This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
    Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
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    ICCAD
    1995
    IEEE
    78views Hardware» more  ICCAD 1995»
    A unified approach to topology generation and area optimization of general floorplans
    13 years 8 months ago
    A unified approach to topology generation and area optimization of general floorplans
    Download  www.cecs.uci.edu
    Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab...
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    ICCAD
    1995
    IEEE
    140views Hardware» more  ICCAD 1995»
    Bounded-skew clock and Steiner routing under Elmore delay
    13 years 8 months ago
    Bounded-skew clock and Steiner routing under Elmore delay
    Download  vlsicad.ucsd.edu
    : We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We presenttwo approachesto construct bounded-skew routing trees: (i) the Boundary Mergin...
    Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-...
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