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ICCAD
1997
IEEE
91views Hardware» more  ICCAD 1997»
13 years 9 months ago
Interconnect layout optimization under higher-order RLC model
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
Jason Cong, Cheng-Kok Koh
ICCAD
1997
IEEE
118views Hardware» more  ICCAD 1997»
13 years 9 months ago
Global interconnect sizing and spacing with consideration of coupling capacitance
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang P...
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
13 years 9 months ago
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
Chen-Huan Chiang, Sandeep K. Gupta
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
13 years 9 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
ICCAD
1997
IEEE
121views Hardware» more  ICCAD 1997»
13 years 9 months ago
Adaptive methods for netlist partitioning
An algorithm that remains in use at the core of many partitioning systems is the Kernighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM...
Wray L. Buntine, Lixin Su, A. Richard Newton, Andr...
ICCAD
1997
IEEE
96views Hardware» more  ICCAD 1997»
13 years 9 months ago
Resource sharing in hierarchical synthesis
This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. Entire subdesigns can efficie...
Oliver Bringmann, Wolfgang Rosenstiel
ICCAD
1997
IEEE
171views Hardware» more  ICCAD 1997»
13 years 9 months ago
The disjunctive decomposition of logic functions
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
Valeria Bertacco, Maurizio Damiani
ICCAD
1997
IEEE
78views Hardware» more  ICCAD 1997»
13 years 9 months ago
A signature based approach to regularity extraction
Regularity extraction is an important step in the design ow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from th...
Srinivasa Rao Arikati, Ravi Varadarajan
ICCAD
1997
IEEE
82views Hardware» more  ICCAD 1997»
13 years 9 months ago
Fast power estimation for deterministic input streams
Luca Benini, Giovanni De Micheli, Enrico Macii, Ma...